Computers are an essential component of modem life. Increasing the speed and efficiency of computers is a common goal being pursued by a variety of companies.
As is generally known, computers use a variety of addressing schemes to access main store memory to retrieve instructions and data. The address actually applied to the main store memory is often referred to as a real address, an effective address is the address actually referred to by programmers, and a virtual address is intermediate to the real address and the effective address.
Because programmers generally refer to an effective address when constructing computer programs, the effective address must be translated first to a virtual address and then to a real address before main store memory can be accessed. To achieve increased computer performance and speed, this address translation process must be efficiently performed.
As mentioned above, many conventional computer architectures first translate the effective address to a virtual address and then translate the virtual address to a real address. The PowerPC.RTM. architecture includes two modes for performing this address translation. In the 32-bit mode, high speed segment registers (SR) are employed to obtain the virtual address by parsing a field in the effective address that specifies one of 16 segment registers, each of which stores a corresponding virtual address. This virtual address is then concatenated with another field of the effective address, hashed, and then utilized to access a translation lookaside buffer (TLB) to obtain the real address.
Another way to perform effective-to-real address translation is to utilize a 64-bit mode, in which a segment ID or tag field of the effective address is utilized to access a segment lookaside buffer (SLB) to obtain the virtual address. This virtual address is then used to access the TLB and thereby obtain the real address.
Each of the above-described effective-to-real address translations involves a two-stage process and consumes valuable processor cycles. A conventional solution to speed up this effective-to-real address translation is to utilize an effective to real address translation cache which stores the most recent translations (e.g., 16 translations per thread or 32 translations for a single-threaded processor). Using an effective-to-real address translation cache skips the two steps of address translation from the effective to virtual address and then from the virtual to the real address. In this way, the processor need only access the effective-to-real address translation cache to obtain the address of the last 16 or 32 translations.
Although an effective-to-real address translation cache can speed up the address translation process, the validity of the translations stored therein must be accurately maintained. During normal address translation or other processing, a page or a segment table may be altered. This alteration must be reflected to the effective-to-real address translation cache to maintain cache integrity. This situation occurs when an instruction such as a move to segment register (MTSR) has been executed. The move to segment register instruction specifies one of the segment registers and changes its value. Because the segment registers map on a segment basis which include a plurality of pages, changing the value stored by the segment register has a cascade-like effect, which renders all corresponding entries in the ERAT stale and inaccurate.
One conventional solution for managing the effective-to-real address translation cache to ensure address translation integrity, is to blindly throw out or discard all of the values in the entire effective-to-real address translation cache upon the occurrence of a move to segment register instruction. However, the performance impact of this conventional solution is severe. Changing all of the valid bits in all of the effective-to-real address translation cache entries to zero is a time-consuming process that severely effects the performance of the computer architecture.
Another conventional solution is to construct the effective-to-real address translation cache with a content addressable memory. With such a construction, when there is a move to segment register instruction, the context addressable logic can specifically identify the corresponding entry in the effective-to-real address translation cache and invalidate the identified entry. Although this conventional solution avoids invalidating the entire effective-to-real address translation cache, the content addressable memory array for implementing the effective-to-real address translation cache is four times larger than a conventionally implemented effective-to-real address translation cache. Furthermore, the context addressable memory logic is quite complex and slow, and thereby reduces the speed of the address translations and negatively affects processor performance.
Therefore, there is a need for efficiently managing an effective-to-real address translation cache which does not require a content addressable memory array and which does not significantly effect processor performance.